Job description
Design Engineer
JD: Implement and support advanced integrated circuits physical design for TSMC’s advanced processing technology, including generate 4 bit adder layout and schematic simulation, perform sign off checks, Verilog hardware design, custom hardware design, dynamic and static power optimization, power and clock design and timing analysis, extraction on the DRC/LVS (Design Rule Checker/Layout vs. Schematic)-clean layout, and verification of functionality using post-layout extracted simulation.
Require: M.S. in Electrical Engineering, or Electrical and Computer Engineering; academic background in 4 bit adder layout and schematic simulation, Verilog hardware design, custom hardware design, dynamic and static power optimization, power and clock design and timing analysis, extraction on the DRC/LVS-clean layout, and post-layout extracted simulation.
Work site/mail resume to: TSMC Technology, Inc., 2851 Junction Ave., San Jose, CA 95134.
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