Job description
Acacia, now part of Cisco, provides innovative silicon-based high speed optical interconnect products to accelerate network scalability through advancements in performance, capacity, and cost. Our DSP ASICs, silicon photonic PICs and coherent modules empower cloud and service providers to meet the fast-growing demand for data. We have assembled a team of cross-functional experts capable of solving the challenges of next generation optical interconnects, resulting in industry-leading, award-winning products. Come join us at Cisco, named the #1 world’s best workplaces, and do purposeful work that makes a global impact and gives back to a company culture that empowers an inclusive future for all.Responsibilities:
Setup and implement MBIST, REPAIR, Boundary Scan, EDT, OCC and SCAN at chip and/or block level
Setup Pattern generation flow for Scan/ATPG & MBIST/Repair/Fuse
Code and own RTL for DFT control logic
Requirements:
Minimum Bachelor’s degree required in Electrical or Computer Engineering
Experience of 5+ years in Design for Test Flows and Implementation
SNPS/Mentor Tessent Shell hands on experience. Good understanding of IJTAG 1687 Structures.
Mush have industry experience implementing Scan control Logic in RTL
Should have good understanding of Scan compression and Scan Partitioning.
Knowledge of clocking architecture during various ATPG modes like Intest and Extest
Experience in MemoryBIST, eFuse, Repair and Yield Improvement techniques
Experience in JTAG Boundary Scan Insertion AC/DC
Scripting experience to automate DFT flows with TCL
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